Retiming of Latches for Power Relduction

In this paper a ret iming methodology i s proposed which reduces the power consumpt ion of digital CMOS circuits. T h e application of high level synthesis tools f o r arbitrary designs usual ly leads to the usage of edge triggered registers. However, VLSI implementa t ions of DSP algorithms which are considered here m a k e level sensi t ive registers applicable. Level sensitive registers consist G$ two latches which store the data for half a clock period. If these latches are placed separately in the circuit then glitching can be reduced and single latches can store data o n the gate capacity of the logic instead of the gate of additional inverters . These two effects reduce the power dissipation of the total circuit and savings of the considered DSP implementa t ion u p to 20 % or more have been achieved.